1. Field of the Invention
This invention relates to bipolar transistors and, in particular, to a bipolar transistor capable of being used in a bipolar memory cell of smaller size than heretofor achieved.
2. Prior Art
Various ways have been proposed to isolate electrically a plurality of pockets of semiconductor material in each of which one or more circuit elements can be formed. Two goals of these various isolation methods have been to reduce the size of the isolation regions in proportion to the total area of silicon available for the formation of active devices and to decrease the size of the active devices. Among the proposed isolation techniques have been appropriately biased PN junctions (Noyce, U.S. Pat. No. 3,117,260, issued Jan. 7, 1964), combinations of PN junctions and zones of intrinsic and extrinsic semiconducting materials (Noyce, U.S. Pat. No. 3,150,299, issued Sept. 22, 1964), dielectric isolation (Frescura U.S. Pat. No. 3,391,023, issued July 2, 1968), mesa etching (Frescura et al. U.S. Pat. No. 3,489,961, issued Jan. 13, 1970) and selectively doped polycrystalline silicon between islands of single crystal silicon of opposite conductivity type (Tucker and Barry U.S. Pat. No. 3,736,193, issued May 29, 1973). A major improvement in packing density was achieved by a method and structure disclosed by Peltzer wherein a thin silicon epitaxial layer was subdivided into electrically isolated pockets by a grid of oxidized regions of the epitaxial silicon material extending through the epitaxial material to an underlying laterally extending isolation PN junction (Peltzer, U.S. Pat. No. 3,648,155, issued Mar. 7, 1972).
Peltzer recognized that the use of diffused regions for isolation and for the formation of active semiconductor devices resulted in larger, less well-defined, circuits than desired for many applications and thus replaced the diffused isolation regions with field oxide.
Smith in U.S. Pat. No. 4,025,364 further improved the Peltzer structure by using ion implantation techniques for simultaneously fabricating epitaxial resistors, base resistors and vertical transistor bases. The result was a further decrease in device size and manufacturing complexity.
Michel et al in U.S. Pat. No. 4,111,720 issued Sept. 5, 1978 disclosed a method for forming a non-epitaxial bipolar integrated circuit. Michel et al first formed recessed silicon dioxide regions in a silicon substrate of one type conductivity. These recessed regions extended into the substrate and laterally enclosed at least one silicon substrate region of one type conductivity. Michel et al then formed by ion implantation a first region of opposite type conductivity fully enclosed laterally by the recessed silicon dioxide (the dopant concentration peak of this first region is below the surface of the first region) and then formed a second region of one type conductivity which extends from the surface into the first region of opposite type conductivity to a point between the concentration peak of this first region and the surface. Finally, Michel et al formed a third region of opposite conductivity type which extended from the surface partway into the second region of one type conductivity. The Michel et al method preferably used an ion beam energy level of at least one MEV with a concentration peak in the first region at least one micron below the surface (Michel et al, column 3, lines 12-14). The silicon dioxide regions were formed about 5 microns into the substrate (Michel Pat. No. 4,111,720, column 3, line 53). The elimination of the epitaxial layer from the structure removed one high temperature process which resulted in a substantial change in location of diffused subcollectors (low resistive conductive paths for carrying the collector current) formed in the substrate beneath the epitaxial layer. Notwithstanding the extensive use of ion implantation, the structure disclosed in the Michel et al patent is still considerably larger in size than required to achieve the packing densities associated with very large scale integrated circuits.
To prevent unwanted channelling between adjacent islands of isolated silicon material, the prior art has in numerous references taught the use of more heavily doped channel stop regions in the semiconductor material underlying the isolation between adjacent islands of silicon material. U.S. Pat. No. 3,748,187 discloses a method for forming a channel stop region wherein a mask is formed over the surface of the wafer, portions of the mask overlying to-be-formed grooves in the underlying silicon material are removed and grooves are formed in the silicon material by a method which under-etches the lateral portions of the masks. The exposed bottoms of the grooves are then implanted with an impurity. The overhangs of the mask extending from the islands of silicon material protect the underlying portions of the grooves from being implanted with the selected dopant. Consequently, the more heavily doped portions of the substrate at the bottom of the grooves are laterally spaced from the diffusions of the active devices (such as sources, drains or emitters and bases) on opposite sides of the to-be-formed field oxide above the more heavily doped regions.
In keeping with the trend toward use of ion implantation techniques, U.S. Pat. No. 3,841,918 on an invention of Argraz-Guerena et al discloses ion implanting impurities through a mask into an epitaxial layer to form a deep collector contact zone having a well-controlled number of impurities and therefore a well-controlled resistivity. However, even this particular process fails to achieve the significant advantages which I have discovered are capable of being achieved using ion implantation techniques.